Method for power routing and distribution in an integrated circuit with multiple interconnect layers

This invention relates to integrated circuits, in particular to integrated circuits that are designed using logic cells selected from a cell library. An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level Ma second set of power buses and on interconnect level Mand a third set of power buses and on interconnect level MThe set of power buses on level Mare oriented in the same direction as the set of power buses on level Mand both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M-Mpower vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M-Mpower vias. Dummy cell with M-Mpower vias is positioned as needed so as not to exceed a maximum strapping distance DA maximum value for distance Dis selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.