System for asynchronously transferring timed data using first and second clock signals for reading and writing respectively when both clock signals maintaining predetermined phase offset

The invention relates generally to the transfer of data using asynchronously timed signals and, more particularly, to a system and method that permits data from an external asynchronously timed system to be infinitely delayed with respect to internal timing. A system is provided to transfer parallel incoming data from an interface device with an external timing domain, for reading in an internal timing domain, without the use of external control signals. System constraints are reduced by permitting an infinite delay to occur in the byte clock timing through the interface device. The system tolerates a specified drift of the byte clock after initialization which may be the result of thermal changes in the interface device, for example. If the specified drift is exceeded, the system is able to reinitialize timing to reestablish the specified byte clock drift, and so continue the transfer of data from the interface device. A method of transferring data using an internal timing domain, from an interface device having an external timing domain, is also provided.