Direct memory access (DMA) receiver

This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system. A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory is provided. The random access memory and DMA receiver being coupled are to a central processing unit by a bus. The central processing unit is coupled to a local cache memory. The source of such data provides an address for the data, such address being the location the random access memory where the data is to be stored. The DMA receiver includes an address register, a first data register and a duplicate data register. The duplicate register has an input coupled to an output of the first data register. A selector is provided having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register. The selector couples one of the pair of inputs to an output thereof selectively in accordance with a select signal. A state machine is included in the DMA receiver. The state machine is responsive to a receive write enable signal from the source. In response to such signal, the state machine loads the address into the address register and loads the data into the first data register transferring the data onto the bus for storage in the random access memory at the address loaded into the address register. The state machine also checks to determine whether the data corresponding to the address being written into the random access memory is currently stored in the local cache memory. The state machine also transfers the data in the first data register into the duplicate data register. If the data is located in the local cache memory, the state machine waits for the central processing unit to copy data in the local cache memory to the addresses in the random access memory, produces the select signal to couple the data in the duplicate data register to the bus, and overwrites the data in the local cache memory with the data provided on the bus by the duplicate data register.