Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate

In general, the present invention relates to a dynamic random-access memory, such as a DRAM. More particularly, the present invention relates to a semiconductor device having a configuration comprising a DRAM and other semiconductor elements, such as a logic circuit. Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.