Method of forming an alignment feature in or on a multilayered semiconductor structure

The present invention relates to integrated circuits and, more particularly, to a method of forming an alignment feature in or on a multi-layered semiconductor structure for aligning a lithography mask and that may be used in connection with a SCALPEL tool. A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.