Testing method and apparatus assuring semiconductor device quality and reliability

The present invention is related in general to the field of semiconductor devices and testing and more specifically to a testing methodology assuring device quality and reliability without conventional burn-in while using a low-cost tester apparatus. An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.