Error correcting latch
This invention relates generally to integrated latch or flip-flop circuits, and, more particularly, to a technique for correcting errors in the output signal of the latch due to single event upsets or on-chip coupling noise. An error-correcting partial latch stage includes a first pass gate having a...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | This invention relates generally to integrated latch or flip-flop circuits, and, more particularly, to a technique for correcting errors in the output signal of the latch due to single event upsets or on-chip coupling noise.
An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling. |
---|