Programmable output generator

This invention relates to microprocessors, and more specifically, to programmable output generators. A memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog conversions, and generating processor interrupts is disclosed. These events are considered high speed since they are timed relative to a high-speed clock and require minimal processor over head. The event generator may be embodied as either a peripheral to a microcontroller or as a separate circuit. In its preferred embodiment, the output generator is a peripheral device on a microcontroller and uses a dedicated programmable, reloadable timer which is inaccessible to other blocks. Events are loaded in a serial format, where only one event is active at a given time. These events are sequenced through address pointers associated with each event. Once a given event is completed, the output generator loads the next event from a next address pointer. The dedicated timer loads one event at a time, counts down to zero, then loads the next event time, counts down to zero, and continues in this manner until disabled, either externally by the CPU or internally as a result of a prescribed next address. The output generator preferably utilizes 64 dual port register blocks organized in program memory which is accessible to both the output generator and the top level CPU or microcontroller. In a data output mode, output generator pin events are byte wide, thereby allowing up to 8 bits to change during each POG event. Other modes can trigger events in other peripherals or generate an interrupt signal for the CPU.