Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching

1. Field of the Invention A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as "masters"). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements. A sort queue may be used to reorder the requests. The result is improved memory access performance.