Method for automating validation of integrated circuit test logic

The presented invention relates generally to the use of test logic hardware to prove out integrated circuit design and, more particularly, to a method for automatic validation of integrated circuit test logic. A methodology for automatic validation of integrated circuit (IC) test hardware that is performed during extraction of the test hardware. Signal connectivity between output test ports of one or more test control blocks and serially-connected scan latches of the test hardware is automatically validated, as is inter-connectivity between the serially-connected scan latches. Every instance to which a test signal and a test data signal at an output test port (both test signal and test data ports) of a test control block fans out to is traversed until a scan latch is reached in order to provide electrical and functional verification of the test hardware.