Data balancing scheme in solid state storage devices

The present invention relates to solid state data storage devices, and particularly although not exclusively, to solid state storage devices having one or more two-dimensional arrays of memory elements. A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of '1's and '0's, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the '1's and '0's are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.