System and method for TLB buddy entry self-timing

This invention relates in general to accessing memory of a computer system, and in particular to a method and system that provide a translation look-aside buffer (TLB) implementing a self-timed evaluation of whether a virtual address for a memory access request is found within the TLB, which reduces the latency involved in accessing the memory to satisfy the memory access request. A self-timed translation lookaside buffer (TLB) is disclosed that utilizes a two-level match scheme to trigger the evaluation of whether a match is achieved for a received virtual address within the TLB. The first level is referred to as the local match, and the second level is referred to as the global match. An entry of a TLB comprises groups of bits, with each group coupled to a separate local match line. Each of the local match lines of an entry is coupled to a global match line, which is initially set to a high voltage level and discharges to a low voltage level if any of the local match lines indicate a mismatch for their respective group. Accordingly, when the global match lines are evaluated, if the global match line has a high voltage level it indicates that the associated TLB entry matches the virtual address, otherwise the global match line indicates a mismatch for the entry. Multiple global match lines are evaluated to trigger a memory access for a matching entry. More specifically, in a preferred embodiment, a pair of neighboring global match lines are input to a NAND gate, the output of which triggers the evaluation of whether a match is achieved for either entry.