System for generating a reference voltage

The present invention is generally directed to integrated circuits and, in particular, to a system for generating a reference voltage. A system for generating a reference voltage is provided that includes a first p-type, thick-gate transistor, a second p-type, thick-gate transistor, a third p-type, thick-gate transistor, and a fourth p-type, thick-gate transistor. The first p-type transistor has a source that is coupled to an external power supply, a gate, and a drain that is coupled to the gate. The second p-type transistor has a source that is coupled to the drain of the first p-type transistor, a gate, and a drain that is coupled to the gate. The third p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive a mode indicator, and a drain that is coupled to ground. The fourth p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive an inverted mode indicator, and a drain that is coupled to ground.