Process of fabricating an integrated circuit

This application is based upon and claims priority from prior French Patent Application No. 0001801, filed on Feb. 14, 2000, the entire disclosure of which is herein incorporated by reference. A process produces at a predetermined metallization level at least one metal track () within an intertrack...

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Bibliographische Detailangaben
Hauptverfasser: Kordic, Srdjan, Torres, Joaquin, Motte, Pascale, Descouts, Brigitte
Format: Patent
Sprache:eng
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Zusammenfassung:This application is based upon and claims priority from prior French Patent Application No. 0001801, filed on Feb. 14, 2000, the entire disclosure of which is herein incorporated by reference. A process produces at a predetermined metallization level at least one metal track () within an intertrack dielectric material (). The process includes the steps of etching the intertrack dielectric material () so as to form a cavity () at the position of the track, depositing a conducting barrier layer () in the cavity (), filling the cavity () with copper, and depositing a silicon nitride layer () on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi() during the diffusion of the silicon from the silicon nitride layer ().