Method for adding decoupling capacitance during integrated circuit design
1. Technical Field A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros....
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| creator | Bernstein, Kerry Cohn, John M Neves, Jose L. P |
| description | 1. Technical Field
A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area. |
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A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6523159$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6523159$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bernstein, Kerry</creatorcontrib><creatorcontrib>Cohn, John M</creatorcontrib><creatorcontrib>Neves, Jose L. P</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Method for adding decoupling capacitance during integrated circuit design</title><description>1. Technical Field
A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZPD0TS3JyE9RSMsvUkhMScnMS1dISU3OLy3IATGTEwsSkzNLEvOSUxVSSotAQpl5JanpRYklqSkKyZlFyaWZJUANxZnpeTwMrGmJOcWpvFCam0HBzTXE2UO3tLgAqDyvpDgeqA9EGZiZGhkbmloaE6EEAL7hNd4</recordid><startdate>20030218</startdate><enddate>20030218</enddate><creator>Bernstein, Kerry</creator><creator>Cohn, John M</creator><creator>Neves, Jose L. P</creator><scope>EFH</scope></search><sort><creationdate>20030218</creationdate><title>Method for adding decoupling capacitance during integrated circuit design</title><author>Bernstein, Kerry ; Cohn, John M ; Neves, Jose L. P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_065231593</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Bernstein, Kerry</creatorcontrib><creatorcontrib>Cohn, John M</creatorcontrib><creatorcontrib>Neves, Jose L. P</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bernstein, Kerry</au><au>Cohn, John M</au><au>Neves, Jose L. P</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for adding decoupling capacitance during integrated circuit design</title><date>2003-02-18</date><risdate>2003</risdate><abstract>1. Technical Field
A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Method for adding decoupling capacitance during integrated circuit design |
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