Method for adding decoupling capacitance during integrated circuit design

1. Technical Field A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros....

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Bernstein, Kerry, Cohn, John M, Neves, Jose L. P
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:1. Technical Field A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.