Method and data processing system for using quick decode instructions

Generally, the present invention relates to instruction decode and execution, and specifically to conditional decoding of instructions. A cache line of a cache () contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit () (CPU) which performs the function associated with the modifiable instruction. After the modifiable instruction has been executed, the CPU () sets an instruction modified bit associated with the cache () based on the execution results of the modifiable instruction. During a subsequent process of the modifiable instruction location, the CPU Decode Unit () substitutes a modified instruction for the modifiable instruction based on the instruction modify indicator.