Variable read/write margin high-performance soft-error tolerant SRAM bit cell

This invention pertains to single or multi-port SRAM bit cells with improved resistance to a-particle strike-induced soft-error or single event upset (SEU) effects. A single event upset (SEU) tolerant SRAM bit cell for six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 m or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell's read and write cycle time and negligible impact on cell stability.