Method for forming a damascene FeRAM cell structure

The present invention is generally related to the fabrication of integrated circuits (ICs) and, more specifically, to the fabrication of a three-dimensional, one transistor/one capacitor (1T/1C), ferroelectric structure. A three-dimensional ferroelectric structure and fabrication method are provided. The ferroelectric capacitor structure permits immediate contact between a noble metal capacitor electrode and a transistor electrode. This direct connection minimizes process steps and electrical resistance between capacitor and transistor. A damascene capacitor electrode formation process makes the task of etching the noble metal less critical. Regardless of whether a noble metal capacitor electrode is used, the damascene formation process permits both larger, and more space efficient, capacitors. Further, the damascene capacitor formation process can be used to simultaneously form electrical interlevel interconnections to the transistor drain. Another variation of the invention provides for a dual damascene version of the ferroelectric capacitor.