Three-dimensional interconnection geometries for multi-stage switching networks using flexible ribbon cable connection between multiple planes

The first related patent application for IMPLEMENTATION OF MULTI-STAGE SWITCHING NETWORKS generally concerns the design of multi-stage interconnection switching networks that provide for the exchange of data between multiple electronic devices, and more particularly concerns the logic organization and layout of semiconductor die, and the associated wiring between such die, for implementing large and very large three-dimensional multi-stage interconnection networks. The multi-stage interconnection networks so designed are characterized by (i) an efficient logical organization, (ii) a very large size that typically interconnects of the order of 4096 and more communication ports, and (iii) a sophisticated, three-dimensional, interconnection geometry. Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred "layered network" of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.