Complementary logic error detection and correction

The present invention relates in general to a system and method for ensuring that a complementary condition is maintained at the output of a complementary logic circuit. In particular, the present invention relates to a system and method that automatically corrects an illegal non-complementary condition at the output of a complementary logic circuit, thereby avoiding the unpredictability and uncertainty that result from a non-complementary output. A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.