Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained

The present invention pertains to a process for manufacturing electronic devices comprising high voltage MOS transistors, and an electronic device thus obtained. A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.