Hierarchical wiring method for a semiconductor integrated circuit

The present invention relates to a wiring method for an implementation design of a semiconductor integrated circuit (IC), and in particular, to a hierarchical wiring method suitable for a hierarchical implementation design in which lower and upper hierarchical layers are employed to hierarchically design a configuration of the semiconductor integrated circuit. In a computer-aided design (CAD) method for the intra-chip wiring in a hierarchical implementation design of a semiconductor integrated circuit, wiring pattern spaces from block edge terminals are guaranteed while preventing any wiring detour in inter-block nets. Logical line connecting information and implementation information such as contours of parts and terminal positions are inputted from a logical file and a library to extract block edge terminals so as to define a block boundary in accordance with layout positions of parts to be allocated. On the block boundary defined, one virtual terminal is generated for each block edge terminal to dispose wirings between the block edge terminals and the associated virtual terminals. An intra-block net wiring is then achieved without a short circuit to the wirings between the block edge terminals and the associated virtual terminals. Finally, the virtual terminals and the wiring pattern between the block edge terminals and the associated virtual terminals are deleted.