High selectivity, low etch depth micro-loading process for non stop layer damascene etch

The present invention relates generally to semiconductor fabrication and more specifically to damascene etch methods. A method for etching a dielectric layer comprising the following steps. A structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CHF/O/N/Ar etch chemistry.