Mechanism for broadside reads of CAM structures

The technical field encompasses computer architectures having content addressable cache designs. In particular, an architecture that supports reading of the contents of the tag portion of a CAM structure without the need for a separate RAM read port. A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a "hit" signal if the selected bit is the same as the corresponding bit of the stored tag value. Storage means are employed for recording the results of the compare with the M hit signal.