Programmable burst FIFO

This invention relates in general to the field of electronics and more particularly to a programmable burst FIFO buffer. A programmable burst FIFO buffer () allows for burst of data to be loaded into memory () without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer () is also programmable and allows for "N" words to be loaded with "N" being programmable in any given burst without having to check for a buffer full condition. The buffer () also avoids the glitches associated with other buffer designs due to the write and read clock being in different domains.