Cavity semiconductor package with exposed leads and die pad

The present invention relates to semiconductor chip packages, and in particular to a cavity semiconductor package with exposed leads and an exposed die pad, and a method for making the same. A semiconductor chip package and a method of making the package are disclosed. The method includes forming a lead frame having a die pad and leads. At least one of the leads has a tab projecting upward and laterally from a body of the lead. In one embodiment, curved tips are formed on the inner ends of the leads. At least a portion of the lead frame is encapsulated with a mold material to form a package mold having a cavity. The cavity has a floor with a thickness substantially similar to the thickness of the leads so as to expose upper surfaces of the inner ends of the leads. The leads have lower surfaces exposed at the lower surface of the package mold. The lead tab is entirely encapsulated within the package mold. A semiconductor die is mounted on the lead frame subsequent to the encapsulation of at least a portion of the lead frame. The semiconductor die is enclosed in the package mold by placing a covering such as a lid over the semiconductor die. This method yields a cavity semiconductor package which may be used in applications where contact between the package mold and the semiconductor die and/or bond wires is undesirable, while allowing the leads and die pad to be securely held in place by the package mold.