Digital phase-locked loop with phase optimal frequency estimation

This invention relates to a read channel for a hard disk drive and more particularly to a digital phase-locked loop with phase optimal frequency estimation. A circuit is designed with a register circuit () arranged to store a control word. A voltage-controlled oscillator () is coupled to receive the control word () and produce a clock signal () having a current frequency corresponding to the control word. A phase detector circuit () is coupled to receive a reference signal () and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal () having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit () is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word () corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.