State management in a co-verification system

The present invention relates to design verification systems. More particularly, the present invention relates to management of co-verification of a target design. A method and apparatus for state management in a co-verification system is described. The invention allows acceleration of co-simulation without loss of information that can occur from independent simulation of software and hardware components of a design. For example, counters included in a hardware component that are influenced by software components are simulated and updated by the software simulator when simulation of hardware and software is not synchronized. When the counter or other hardware component that is maintained by software simulation causes a hardware event (e.g., an interrupt) to occur, co-simulation is resynchronized and the hardware component is updated. Improved acceleration of co-simulation is thereby provided.