Test pattern generator, propagation path disconnecting method, and delay fault detecting method

The present invention relates to a test pattern generator used at the time of developing an LSI, a loop disconnecting method, a propagation path disconnecting method, a delay fault detecting method, and a computer-readable recording medium recorded with a program for making the computer execute these methods. More particularly, this invention relates to a test pattern generator for detecting a stack fault or a delay fault by a scan test method, a loop disconnecting method, a propagation path disconnecting method, a delay fault detecting method, and a computer-readable recording medium recorded with a program for making the computer execute these methods. A test pattern generator for automatically generating a test pattern for detecting a stack fault of a large scale integrated circuit an LSI with a tester includes a loop/path disconnecting section for disconnecting a loop portion of the LSI at a position where a fault detection rate is not lowered, based on net list information of the LSI and constraint of a test design rule when automatically generating the test pattern. A test pattern generator increasing fault detection rate and carrying out a suitable test is obtained.