Method and apparatus for measuring effects of packaging stresses of common IC electrical performance parameters at wafer sort

1. Field of the Invention In the testing of one or more die as part of a semiconductor wafer, electrical testing of an unstressed die of a wafer is undertaken. The die of the wafer is then physically stressed to a first stressed state, and electrical testing is undertaken thereon. The die of the wafer is then physically stressed to a second stressed state, and electrical testing is again undertaken on the die as it is in its second stressed state. The results of the tests are compared and extrapolated to indicate electrical performance of the die in other physically stressed states. A relatively simple tool is provided for use in performing in this method in an effective and rapid manner.