Chip-on-chip testing using BIST

The present invention relates to a novel and useful method for testing a chip-on-chip semiconductor device and a novel chip-on-chip device which implements this method. An auxiliary BIST circuit is constructed in a primary chip to which a secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit. This allows direct test access to the secondary chip without the need for a separate BIST circuit to be included in the secondary IC chip and without using a primary BIST circuit of the primary IC chip to test the secondary chip.