Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics

The invention is generally related to the field of forming interconnect layers in integrated circuits and more specifically to dual damascene interconnect processes with Cu and low-k dielectrics. A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via () etch, a trench () is etched in the OSG layer () using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N/Ar ratio. The low N/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.