Interleaved memory device for sequential access synchronous reading with simplified address counters

The present invention relates in general to memory devices, and, in particular, to an interleaved memory device readable in a synchronous mode for successive locations with a sequential or burst access mode. An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.