Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
1. Field of the Invention An integrated circuit contains a central processing unit ("CPU"), a graphic control hub ("GCH"), a memory control hub ("MCH"), and a phase lock loop ("PLL"). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transa...
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| Sprache: | eng |
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