Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems

Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems

1. Field of the Invention An integrated circuit contains a central processing unit ("CPU"), a graphic control hub ("GCH"), a memory control hub ("MCH"), and a phase lock loop ("PLL"). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Jain, Satchit, Cho, Sun-Soo
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:1. Field of the Invention An integrated circuit contains a central processing unit ("CPU"), a graphic control hub ("GCH"), a memory control hub ("MCH"), and a phase lock loop ("PLL"). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.