Method and apparatus for in-situ testing of integrated circuit chips

The invention relates to integrated circuit chip testing. Typically, integrated circuit chips are attached to a chip carrier, thermally conductive module chip carrier, circuit card or board, e.g., by solder bonding, controlled collapse chip connect, or the like. For the first time since the wafer wa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Bhatt, Anilkumar Chinuprasad, Buda, Leo Raymond, Edwards, Robert Douglas, Hart, Paul Joseph, Ingraham, Anthony Paul, Markovich, Voya Rista, Molla, Jaynal Abedin, Murphy, Richard Gerald, Saxenmeyer, Jr., George John, Walker, George Frederick, Whalen, Bette Jaye, Zarr, Richard Stuart
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The invention relates to integrated circuit chip testing. Typically, integrated circuit chips are attached to a chip carrier, thermally conductive module chip carrier, circuit card or board, e.g., by solder bonding, controlled collapse chip connect, or the like. For the first time since the wafer was diced, the chip is tested, e.g., electrically tested and logically tested. Some of the tests are subtle, for example tests for active and passive pattern faults and "stuck at 1" or "stuck at 0" faults. When a fault is found, the chip is removed from the card or board. This is not a simple "desoldering" step, especially in the case of high I/O density integrated circuit chips, bonded with encapsulation chip connect technologies, and usually present in multi-chip modules. When a chip is found to be defective, it must be removed, the chip site redressed, and a new chip installed for testing. In the case of a polymeric substrate, redressing the chip site might include milling. A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.