Method and apparatus for providing probe based bus locking and address locking

The invention relates generally to a method and apparatus employing multiple processors, and more particularly to a method and apparatus for facilitating access to shared memory addresses over a common bus by a plurality of data processors. A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.