Reconfigurable multiplier array

This application is a National Stage application under 35 U.S.C. §371 of International Application No. PCT/GB/03902, which both designated and elected the United States, and claims priority to Great Britain Patent Application No. 9727414.6, filed Dec. 29, 1997. This invention provides a logic block comprising an mxn array of partial calculating circuits (where m 2 and n 2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.