Electrostatic discharge protection circuit

This application claims the priority benefit of Taiwan application serial no. 89104921, filed Mar. 17, 2000. An electrostatic discharge (ESD) protection circuit. A first NMOS transistor has a drain terminal connected to an I/O pad and a gate terminal connected to a voltage source. A second NMOS transistor has a drain terminal connected to a source terminal of the first NMOS transistor and a source and a gate terminal connected to a ground voltage. A third NMOS transistor has a source terminal connected to the I/O pad, a drain terminal connected to the voltage source and a gate and a substrate terminal connected to the ground voltage. A first PMOS transistor has a drain terminal connected to the ground voltage and a substrate terminal of the second NMOS transistor, a source and a substrate terminal connected to the I/O pad and a gate terminal connected to the voltage source. And, a second PMOS transistor has a source and a gate terminal connected to the voltage source, a drain terminal connected to the I/O pad and a substrate terminal connected to a drain terminal of the third NMOS transistor. Under ESD stress conditions, the cascode parasitic BJT can be turned on in advance by triggering a substrate, so that the ESD protection ability can be thus improved.