Multilevel circuit implementation for a tristate bus

The present invention relates to a method and/or architecture for tristate busses generally and, more particularly, to a method and/or architecture for a multilevel circuit implementation for a tristate bus. An apparatus comprising a first circuit and a second circuit. The first circuit may be confi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Ighani, Ramin, Nayak, Anup
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present invention relates to a method and/or architecture for tristate busses generally and, more particularly, to a method and/or architecture for a multilevel circuit implementation for a tristate bus. An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to drive a first bus in response to a first control signal. The second circuit may be configured to control a voltage of the first bus in response to the first control signal.