Fully recessed semiconductor method for low power applications

The subject matter of this application is related to the subject matter of commonly-assigned U.S. patent applications having the following serial numbers and titles: Ser. No. 09/052,059, "Fully Recessed Semiconductor Device and Method"; and Ser. No. 09/052,060, "Fully Recessed Semiconductor Device and Method for Low Power Applications With Single Wrap Around Buried Drain Region", all concurrently filed herewith. A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench. The buried source region and the buried drain region have a depth slightly less than the depth of the trench. In one embodiment, the buried source and buried drain region have asymmetrical depths that are both approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.