Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage

The present invention generally relates to pipeline analog to digital (A/D) converters and, more particularly, to circuit and timing at the initial stages of the pipeline A/D converters. A pipeline analog to digital (A/D) converter. The pipeline A/D converter having a sample and hold amplifier stage, the sample and hold amplifier stage sampling an analog input signal during a first clock pulse signal. The pipeline A/D converter having an analog signal converter stage, the analog signal converter stage sampling the analog input signal during a first clock pulse signal. According to another aspect of the invention, the pipeline A/D converter converts an analog input signal into a digital representation of the analog input signal. The pipeline A/D converter has a clock generator, the clock generator generating a first clock pulse signal, a second clock pulse signal and a third clock pulse signal. A sample and hold stage samples an analog input signal during the pulse of the first clock signal and holds a sampled voltage signal during the pulse of the second clock signal. A first analog signal converter stage converts and latches the sampled and held voltage signal into a digital output during the pulse of the second clock signal, a most significant bit of the digital representation of the analog input signal being derived from the digital output. The first analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output. The first analog signal converter stage sampling the analog input signal during the pulse of the first clock signal and holding the residue signal during the pulse of the third clock signal.