System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch

The present invention relates generally to a superscalar processor and more particularly to the decode and routing of internal instructions to an asymetrical dispatch bus (that is not all instructions can be decoded/dispatched/executed for each and every slot) in such a processor. A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.