Method and apparatus for testing errors in microprocessors

In an advanced multi-core processor architecture, an apparatus and corresponding method, are used to test lock step performance. The apparatus is implemented on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic of each of the two or more processors. A processor-specific resource is referenced by the code sequence, and a state machine asserts a signal based on the occurrence of a programmable event. The apparatus includes an output to provide the asserted signal; and a lock step logic block operates to read and compare the output of each of the more processors. The apparatus may be used to repeatedly and deterministically provide errors that may lead to a loss of lock step.