Apparatus and methods for providing enhanced redundancy for an on-die cache
Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array. |
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