Semiconductor memory device with an improved memory cell structure and method of operating the same

A semiconductor memory device includes a plurality of memory cells, each of which comprises a single pair of a volatile memory element and a non-volatile memory element, wherein the volatile memory element and the non-volatile memory element are electrically coupled to each other, and wherein the volatile memory element is also electrically coupled to a first bit line for transmitting a first bit signal, while the non-volatile memory element is also electrically coupled to a second bit line making a single pair with the first bit line for transmitting a second bit signal which is an inversion to the first bit signal.