Latency time switch for an S-DRAM

Latency time circuit for an S-DRAM ( 1 ), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path ( 38 ) of the S-DRAM ( 1 ), having a controllable latency time generator ( 57 ) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which [lacuna] a comparison circuit ( 60 ) which compares a cycle time (t cycle ) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path ( 38 ), and reduces the latency time of the latency time generator ( 57 ) by the cycle time if the signal delay time of the data path ( 38 ) is greater than the cycle time (t cycle ) of the clock signal (CLK)