Method and apparatus for controlling power states in a memory device utilizing state information

A method of controlling power states in a memory device includes determining if a power-down command is issued. A first lower power state is entered if the power-down command is issued and the memory device is in a first state. A second lower power state is entered if the power-down command is issue...

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Hauptverfasser:	Khandekar, Narendra, Dodd, James
Format:	Patent
Sprache:	eng
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creator	Khandekar, Narendra Dodd, James
description	A method of controlling power states in a memory device includes determining if a power-down command is issued. A first lower power state is entered if the power-down command is issued and the memory device is in a first state. A second lower power state is entered if the power-down command is issued and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not issued.
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fullrecord	<record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20030182588</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20030182588</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200301825883</originalsourceid><addsrcrecordid>eNqVzbEKwkAQBNA0FqL-w7YWQkwQ0otiY2cfl2SjC3e3x-1G0a_3DP6AxTDNY2ZeXM9kd-kBQ06MmNBGhUESdBIsiXMcbhDlSQnU0EiBAyB48pJe0NODO4LR2PH7KyeTSV7waCxhWcwGdEqrXy-K9fFw2Z82o8ZMg2mbfx13k9a2Ksu63DbVrmnqf-wHgyRFAA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for controlling power states in a memory device utilizing state information</title><source>USPTO Published Applications</source><creator>Khandekar, Narendra ; Dodd, James</creator><creatorcontrib>Khandekar, Narendra ; Dodd, James</creatorcontrib><description>A method of controlling power states in a memory device includes determining if a power-down command is issued. A first lower power state is entered if the power-down command is issued and the memory device is in a first state. A second lower power state is entered if the power-down command is issued and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not issued.</description><language>eng</language><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030182588$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,778,871,883,64040</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/10104676$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Khandekar, Narendra</creatorcontrib><creatorcontrib>Dodd, James</creatorcontrib><title>Method and apparatus for controlling power states in a memory device utilizing state information</title><description>A method of controlling power states in a memory device includes determining if a power-down command is issued. A first lower power state is entered if the power-down command is issued and the memory device is in a first state. A second lower power state is entered if the power-down command is issued and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not issued.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNqVzbEKwkAQBNA0FqL-w7YWQkwQ0otiY2cfl2SjC3e3x-1G0a_3DP6AxTDNY2ZeXM9kd-kBQ06MmNBGhUESdBIsiXMcbhDlSQnU0EiBAyB48pJe0NODO4LR2PH7KyeTSV7waCxhWcwGdEqrXy-K9fFw2Z82o8ZMg2mbfx13k9a2Ksu63DbVrmnqf-wHgyRFAA</recordid><startdate>20030925</startdate><enddate>20030925</enddate><creator>Khandekar, Narendra</creator><creator>Dodd, James</creator><scope>EFI</scope></search><sort><creationdate>20030925</creationdate><title>Method and apparatus for controlling power states in a memory device utilizing state information</title><author>Khandekar, Narendra ; Dodd, James</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200301825883</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Khandekar, Narendra</creatorcontrib><creatorcontrib>Dodd, James</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khandekar, Narendra</au><au>Dodd, James</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for controlling power states in a memory device utilizing state information</title><date>2003-09-25</date><risdate>2003</risdate><abstract>A method of controlling power states in a memory device includes determining if a power-down command is issued. A first lower power state is entered if the power-down command is issued and the memory device is in a first state. A second lower power state is entered if the power-down command is issued and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not issued.</abstract><oa>free_for_read</oa></addata></record>
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title	Method and apparatus for controlling power states in a memory device utilizing state information
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T15%3A01%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFI&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Khandekar,%20Narendra&rft.date=2003-09-25&rft_id=info:doi/&rft_dat=%3Cuspatents_EFI%3E20030182588%3C/uspatents_EFI%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true