Simulation method and apparatus for verifying logic circuit including processor

When a model of a logic circuit including a processor is simulated by a simulator for its verification, an error detection process is performed by checking the internal bus of the processor each time the simulator allows the processor to execute one command (S1, S5, S7, S9, S11, S13, S15, and S17). When an error is detected, the error is classified to output its error code and perform a memory dump (S3), and then an abnormal signal is output (S4). In response to this signal, the simulator ends the simulation.